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TI-2017-11033 Aliases CVE-2017-15031GHSA-rmx5-9qww-3c2x

In all versions of ARM Trusted Firmware up to and including v1.4, not initializing or…

Priority LOW 37CWE-200Published · Updated

Key facts

Attack vector
Network
Privileges required
None
User interaction
None
Attack complexity
Low
Impact type
Information disclosure
Confidentiality · integrity · availability
High · None · None
Fix status
No fix listed

Attack profile from CVSS 3.1 · NVD. Fix status from CNA. Impact type from CWE-200.

Summary

In all versions of ARM Trusted Firmware up to and including v1.4, not initializing or saving/restoring the PMCR_EL0 register can leak secure world timing information.

Why it matters now

EPSS 0.01941 80th percentileScored 2026-11-07
Fix No fix listed No fixed version in the sources yet

SSVC decision points

Not available: CISA has not published SSVC decision points for this record.

Affected products

VendorProductAffected versionsFixed inStatusSource
——all versions—No fix listedCNA
  • — Vendor— Affected all versions Fixed in — No fix listed CNA

CPE configurations NVD · 1

CPEVersionsRoleVendor
cpe:2.3:o:trustedfirmware:trusted_firmware-a:*:*:*:*:*:*:*:*up to 2.1VulnerableOP-TEE
  • cpe:2.3:o:trustedfirmware:trusted_firmware-a:*:*:*:*:*:*:*:* Versions up to 2.1 Vulnerable ·OP-TEE

Remediation

No fixed version listed by the sources yet.

Timeline

  1. 2026-10-02 Threatist record created from CVE-2017-15031
  2. 2026-10-03 Alias added: GHSA-rmx5-9qww-3c2x

References

Patch 1

  • TI-2017-05204 In ARM Trusted Firmware 1.3, RO memory is always executable at AArch64 Secure EL1… CVSS 3.1HIGH 8.1
  • TI-2017-05205 In ARM Trusted Firmware through 1.3, the secure self-hosted invasive debug interface… CVSS 3.1HIGH 7.5
  • TI-2022-23658 Trusted Firmware-A through 2.8 has an out-of-bounds read in the X.509 parser for parsing… CVSS 3.1HIGH 7.4
  • TI-2017-07008 The BL1 FWU SMC handling code in ARM Trusted Firmware before 1.4 might allow attackers to… CVSS 3.1HIGH 7.0
  • TI-2018-13763 ARM Trusted Firmware-A allows information disclosure. CVSS 3.1MEDIUM 5.3
  • TI-2023-15001 Improper input validation in AMD Zynq™ UltraScale+™ MPSoC/RFSoC CVSS 3.1MEDIUM 5.8

Sources

This product uses the NVD API but is not endorsed or certified by the NVD. Sources and licences