x86/AMD: missing IOMMU TLB flushing
Key facts
- Attack vector
- Local
- Privileges required
- Low
- User interaction
- None
- Attack complexity
- Low
- Impact type
- —
- Confidentiality · integrity · availability
- High · High · High
- Fix status
- No fix listed
Attack profile from CVSS 3.1 · CISA ADP. Fix status from CNA.
Summary
The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
Why it matters now
SSVC decision points
CISA ADP · SSVC 2.0.3
- Exploitation
- None
- Automatable
- No
- Technical impact
- Total
The decision (Track, Attend, Act) also depends on your mission and well-being impact; see CISA's SSVC guide.
Affected products
Remediation
No fixed version listed by the sources yet.
Timeline
- 2026-10-02 Threatist record created from CVE-2023-34326
- 2026-10-03 Alias added: GHSA-mjvw-frxx-6hm5
References
More Xen vulnerabilities
- TI-2012-00210 The x86-64 kernel system-call functionality in Xen 4.1.2 and earlier, as used in Citrix… CVSS 2.0HIGH 7.2
- TI-2023-07042 Information disclosure through error messages in AMD Ryzen™ 3000 Series Desktop… CVSS 3.1MEDIUM 5.5
- TI-2015-04333 The C+ mode offload emulation in the RTL8139 network card device model in QEMU, as used… CVSS 2.0HIGH 9.3
- TI-2015-06741 The KVM subsystem in the Linux kernel through 4.2.6, and Xen 4.3.x through 4.6.x, allows… CVSS 3.1CRITICAL 10.0
- TI-2018-06436 A statement in the System Programming Guide of the Intel 64 and IA-32 Architectures… CVSS 3.0HIGH 7.8
- TI-2024-20522 x86: Incorrect logic for BTC/SRSO mitigations CVSS 3.1HIGH 7.5
Sources
- CVE-2023-34326 · CVE Program
- CVE-2023-34326 · NVD
- FIRST EPSS
- GHSA-mjvw-frxx-6hm5 · GitHub Advisory Database · CC BY 4.0
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