A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where…
Key facts
- Attack vector
- Network
- Privileges required
- Low
- User interaction
- None
- Attack complexity
- Low
- Impact type
- Privilege escalation
- Confidentiality · integrity · availability
- High · None · None
- Fix status
- No fix listed
Attack profile from CVSS 3.1 · CISA ADP. Fix status from CNA. Impact type from CWE-266.
Summary
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Why it matters now
SSVC decision points
CISA ADP · SSVC 2.0.3
- Exploitation
- None
- Automatable
- No
- Technical impact
- Total
The decision (Track, Attend, Act) also depends on your mission and well-being impact; see CISA's SSVC guide.
Affected products
| Vendor | Product | Affected versions | Fixed in | Status | Source |
|---|---|---|---|---|---|
| — | — | all versions | — | No fix listed | CNA |
- — Vendor— Affected all versions Fixed in — No fix listed CNA
CPE configurations NVD · 1
| CPE | Versions | Role | Vendor |
|---|---|---|---|
| cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:* | up to 1.6 | Vulnerable | Chipsalliance |
- cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:* Versions up to 1.6 Vulnerable ·Chipsalliance
Remediation
No fixed version listed by the sources yet.
Timeline
- 2026-10-02 Threatist record created from CVE-2025-63384
- 2026-10-03 Alias added: GHSA-g435-j3hg-9vfh
References
Sources
- CVE-2025-63384 · CVE Program
- CVE-2025-63384 · NVD
- FIRST EPSS
- GHSA-g435-j3hg-9vfh · GitHub Advisory Database · CC BY 4.0
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